1. Field of Art
The disclosure generally relates to the field of electronic design automation (EDA), and more specifically to routing of power rails for a standard cell that is used to design integrated circuits (ICs).
2. Description of the Related Art
Computer-aided cell-based design has been developed for quickly designing large scale ICs such as application specific integrated circuits (ASICs) and gate arrays. The cell is a circuit that has been pre-designed and pre-verified as a building block. Design technologies known as standard cell and gate array use different types of such building blocks. In a standard cell design, each distinct cell in a library may have unique geometries of active, gate, and metal levels. With gate arrays, however, each gate array cell shares the same building block, called a core cell that includes fixed active and gate level geometries. Different gate array cells are implemented using only metal interconnections between the active and gate elements of one or more core cells. Examples of a standard cell or gate array cell include an inverter, a NAND gate, a NOR gate, a flip flop, and other similar logic circuits.
During the process of designing an integrated circuit, a designer may select particular cells from a library of cells and use them in a design. The library includes cells that have been designed for a given integrated circuit (IC) manufacturing process, such as complementary metal oxide semiconductor (CMOS) fabrication. The cells generally have a fixed height but a variable width, which enables the cells to be placed in rows. Cells do not change from one design to the next, but the way in which they are interconnected will, to achieve the desired function in a given design. By being able to select the cells from the library for use in the design, the designer can quickly implement a desired functionality without having to custom design the cells. The designer will thus have a certain level of confidence that the integrated circuit will work as intended when manufactured without having to worry about the details of the individual transistors that make up each cell.
Cell based designs have power rails that supply voltage potentials such as VDD or VSS to the cells. The VDD or VSS power rails may be disabled during a standby mode to conserve power. For quick wake-up from standby mode, some cells are retention registers that save state information during standby. In standby mode, the retention registers are powered by a retention voltage that remains on even though the primary supply voltage is disabled. Retention registers may be placed unconstrained throughout the integrated circuit which requires the retention voltage to be routed on a retention rail across every cell row for optimum routing efficiency.
Conventional cells are designed with the primary power rails (e.g., VDD and VSS) at the top and bottom boundaries of the cells, which allows the power rails to be shared between adjacent rows of cells. Some designs contain two power supplies: the primary supply VDD, which can be turned off to save power when the block is inactive, and a retention supply VDDR, which is always on. The retention supply is used to save the state of a block when the primary supply VDD is turned off, so that when it is turned back on, it can resume operation without having to reset its state and begin from scratch. The power rail carrying the retention voltage (“retention rail”) is routed across the interior of the cell so that each row of cells has its own dedicated retention rail. However, adding a dedicated retention rail to a cell increases the cell height or takes away a routing track which could otherwise be used to route global signals for connecting the pins of the cells. Additionally, having a retention rail dedicated to just one row of cells is wasteful because retention rails only carry a fraction of the current of a primary power rail such as VDD.